Title: Chiplets - Optimized Device Integration, SWaP Performance & Time-to-Market
Date/Time: May 1st, 2025 at 11am ET
With the current growth of the defense and space systems market accelerating, the high-reliability microelectronics required for these systems are under ever-increasing pressure to consume less size, weight, power, and cost (SWaP-C), as well as to provide increased performance, indefinite product life-cycle sustainability, and supply chain reliability. Challenges in sourcing high-reliability microelectronics include product availability, along with PCN/ECN and obsolescence issues; increased risk with each supplier needed to source the many devices required for the IC; and rising geopolitical tensions with the potential for supply chain disruptions. Packaged IC manufacturing, aside from ASICs, requires multiple devices and interconnects to produce. With many devices to procure, coordinating IC design and manufacture is often fraught with challenges to overcome, including varying leads times as well as PCN/ECN and obsolescence issues. Additionally, multi-supplier procurement for in-house manufacturing requires coordination with multiple sources at various volumes, requiring inspection, testing, and potentially heterogeneous integration. Is there a better solution to minimize supply chain risks, optimize SWaP-C savings and performance, while also accelerating development and production time?
Chiplets, the next generation of System in Package (SiP) microelectronics, enable the most compact and efficient microelectronics solutions to be created through the integration of multiple devices and functions into a single SWaP-C and performance optimized package.
In this webinar, we will explore how Chiplets efficiently address today's market needs, highlight the key points to be considered with a Chiplet solution, and provide insight into the current state of Chiplets, which have not settled on one industry-wide standard for interconnects, communication protocols, and packaging. Experts in BEOL processing, advanced 2.5/3D heterogenous integration, testing, and component packaging will present the latest developments, standards, protocols, and Chiplet design methodology. Attendees will gain deep insight into the considerations and best practices in leveraging the value and performance of Chiplets for high-reliability systems.
Featured Speakers:
John Lannon
General Manager at Micross Advanced Interconnect Technology
Dr. John Lannon (‘91 BS WVU/‘96 PhD WVU in Physics) is the General Manager of Micross Advanced Interconnect Technology. He has worked on the fabrication and improvement of resistive IR emitter devices (a MEMS-like device) for Infrared Scene Projectors for over 20 years. Since 2005, he has assisted with the development of high-density interconnects (sub-20 µm pitch) for die stacking and detector hybridization and the development of wafer-level vacuum packaging (WLVP) of MEMS devices. As part of Micross, he continues to be focused on the development and implementation of 3D integration and advanced packaging technologies (flip-chip bumping, high density interconnect bonding, WLVP, through-Si vias (TSV), through glass via (TGV), Si interposers, etc.) for government and commercial applications, as well as the development of novel 3D microstructures. John is an active member of the WLP Symposium (formerly IWLPC) planning committee, serving as 3D Integration and Packaging Track Chair in 2020 and 2022.
Sultan Lilani
Director of Technical Support, Business Dev. at Integra Technologies
Sultan Ali Lilani is Director of Technical Support, Business Development at Integra Technologies, a Micross company. Prior to joining Integra Technologies, Sultan held a similar position at Silicon Turnkey Solutions (STS). Previous to STS, Sultan was Director of Quality and Reliability at NEC Electronics for 18 years.. Sultan has in-depth knowledge of Reliability Engineering, Program Management, Testing and Qualification for Aerospace, Defense and Industrial applications for semiconductor products including Digital, Analog, Mixed Signal, ASICs, Microprocessors, Memory, Custom Semiconductors, Discretes, Linears and Passives. Sultan is the co-chair of the CE-12 Solid State Devices Committee that develops solutions to technical problems in the application, standardization, and reliability of solid state devices. He is very active in various JEDEC and SAE CE-12 technical committees that develop standard for solid state devices. This includes the ATM task team (Advanced Technology Microcircuit) intended to bring chiplets and heterogeneous integrated (HI) components into the military specification (QML) arena.
John Bowling
Director of Engineering at Micross Silicon Turnkey Solutions
John is the Director of Engineering for Micross’s Silicon Turnkey Solutions Division in Milpitias, California. Prior to joining Micross in December of 2024, John spent over 25 years at Intel Corporation, working on Itanium and XEON Server Chip Design, Design for Test, and Post Silicon Test. John gained expensive experience with chiplets as the manufacturing Chief Engineer of a disaggregated XEON Server product.
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