OCTAVA, MIL-STD-1553 RT/BC/Monitor


Sital’s OCTAVA MIL-STD-1553 devices integrate a Bus Controller (BC) / Remote Terminal  (RT) / Bus Monitor (MT) or RT-only MIL-STD-1553B protocol engine, memory management, processor interface logic, 4K or 64K words of RAM and dual 1553 transceiver in a 72-pad QFN package. The OCTAVA™ is a pin-to-pin replacement for DDC’s® BU-6174X/61864X/6186X Enhanced Mini-ACE® family, providing electrical, mechanical and architectural compatibility.




Part Number Mode Memory Organization Supply Voltage RFQ RFI Tech Support
OCT-61743 RT-only 4K x 16 RAM 5V transceiver, 3.3V logic RFQ RFI Tech Support
OCT-61745 RT-only 4K x 16 RAM 5V transceiver, 5V logic RFQ RFI Tech Support
OCT-61843 BC/RT/Monitor 4K x 16 RAM 5V transceiver, 3.3V logic RFQ RFI Tech Support
OCT-61845 BC/RT/Monitor 4K x 16 RAM 5V transceiver, 5V logic RFQ RFI Tech Support
OCT-61864 BC/RT/Monitor 64K x 17 RAM 5V transceiver, 3.3V logic, 5V RAM RFQ RFI Tech Support
OCT-61865 BC/RT/Monitor 64K x 17 RAM 5V transceiver, 5V logic, 5V RAM RFQ RFI Tech Support



Over the past ten years, Sital has supplied thousands of OCTAVAs which have been flying in military systems.

OCTAVA is supplied with an asynchronous local bus host interface similar to DDC’s, operating into internal registers and either 4K x 16 or 64 K x 17 of shared RAM. The 64 K x 17 version also provides parity generation and checking on all host and internal (1553) accesses.

The OCTAVA’s bus controller (BC) includes a 29-instruction set providing a high degree of processor offloading by automating message scheduling, asynchronous message insertion, facilitating bulk data transfers and double buffering, message retry and bus switching strategies, data logging, fault reporting and issuing host interrupts. The 29 instructions include all 20 of the DDC Enhanced Mini-ACE instructions plus 9 additional instructions. The BC also includes a General Purpose Queue which can be used for stacking information regarding interrupt conditions or other user data.

To support a variety of 1553 Remote terminal (RT) application requirements, the OCTAVA RT provides programmable options for single, double and circular subaddress buffering, along with a global circular buffer option that can be used for multiple (or all) receive or broadcast subaddresses. To further offload the host, the circular buffer options provide interrupts for 50% and 100% rollover conditions. For stacking of interrupt events, OCTAVA’s RT also includes an Interrupt Status Queue.

The OCTAVA bus Monitor enables incoming messages to be filtered based on their RT Address, T/R bit and subaddress and includes its own Interrupt Status Queue.

The OCTAVA is multiprotocol, supporting MIL-STD-1553A, MIL-STD-1553B, STANAG-3838 and General Dynamics 16PP303, along with McAir A3818, A5232 and A5690.

Sital’s MIL-STD-1553 transceivers consume and dissipate extremely low power, with the transmitter dissipating less than 300 mW at 100% transmit duty cycle. Sital’s transmitter also includes a unique, real-time feature to minimize or eliminate residual voltages, aka dynamic offset (or “tails”) at the end of 1553 message transmissions.

For applications involving McAir protocols, Sital can supply OCTAVAs with transceivers providing compatibility with the McAir A3818, A5232 and A5690 standards.

The OCTAVA BC also includes an option (that defaults to "off") for detecting messages transmitted by a "spoofing" (impersonating) BC. If such messages are detected, they are reported to the BC's host processor. The BC includes an additional option for providing intrusion protection (IPS). If this option is activated, the BC will invalidate an impersonating message by transmitting a superceding message on the alternate bus from the impersonating message.

The OCTAVA is available in industrial (-40 to +100° C) temperature range. For military temperature range versions (-55 to +125° C), please contact Sital.




  • MIL-STD-1553B Notice 2, MIL-STD-1553A and MIL-STD-1760 compliant terminals
  • Very fast access 4Kx16, 8Kx16 or 64Kx16 shared RAM
  • Second Source to DDC® Enhanced Mini-ACE
  • Asynchronous local bus host interface. Available with options for high-performance parallel interface, PCI Express, high-performance synchronous PCI or SPI interface
  • Transceiver with very low transceiver power dissipation and built-in real-time transmitter “tails” compensation to eliminate residual voltages (dynamic offset).
  • Register/memory architecture and functionality compatible with DDC® Enhanced Mini-ACE®, Mini-ACE Mark3®, Micro-ACE(TE)® and Total-ACE®
  • Highly autonomous BC with 29 instructions, condition flags and general purpose queue
  • Automatic BC Retry
  • Programmable BC Gap Times
  • Programmable BC Message Rate
  • BC detection of impersonating BC, with option to invalidate impersonating messages
  • Programmable illegalization
  • For RT mode, single, double and circular buffering options
  • Selective Monitor mode with filtering and programmable option for storing monitored data in IRIG-106 Chapter 10 file format
  • 50% Rollover Interrupts for RT and Monitor Stacks & Circular Buffers
  • Bootable RT option required for MIL-STD-1760
  • Simultaneous RT/MT mode
  • Operates from 10, 12, 16 or 20 MHz
  • 72 Pins PQFP 1 x 1-inch package 
  • Available in -40 to 100° C temperature range. For -55 to 125° C, consult Sital


Privacy Policy

By using this online service you accept the handling of any personal data in accordance with the Privacy Policy.