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3D ASIP 2017 Conference

Micross Advanced Interconnect Technology (AIT) Selected to Present at

3D ASIP 2017 Conference, December 5th in San Francisco

 

FOR IMMEDIATE RELEASE

 

Orlando, FL, November 30, 2017 – Micross announces that they’ve been selected to present at the 14th Annual 3D ASIP (Architectures for Heterogeneous Integration & Packaging) Conference on December 5th being held at the Marriott San Francisco Airport. This invitation-only program highlights 2.5/3D enabled applications; high density fan-out; image sensor technology; advanced assembly technology; µbumping & copper pillar technology, equipment and materials which parallels closely with AIT’s extensive range of capabilities.

 

On Tuesday, December 5th, Session 2 on Micro Bumping and Copper Pillar Technology is being chaired by Alan Huffman, Micross AIT Director of Engineering as well as another presentation on High Density Interconnect Bonding at 10um Pitch & Below Using Non-Collapsible Microbumps being given by Matt Lueck, Micross AIT Development Engineer.

 

“We are honored to have this opportunity to showcase Micross AIT’s broad portfolio of advanced interconnect technology solutions during the conference,” said Alan Huffman, Director of Engineering. “As one of the premier wafer bumping and wafer level packaging facilities based in the U.S., we will continue to display and deliver the latest next-gen interconnect and 3D integration technologies to customers around the world.“

 

Micross AIT’s ITAR-registered facility supports wafer sizes up to 200mm with established, automated and proven processes plus the flexibility to tailor unique solutions for the most demanding interconnect requirements.  The facility can also support the processing of non-standard materials, as well as the unique ability to support early stage development needs & low-to-mid volume production for more mature applications and platform technologies. For more information: www.micross.com

 

About Micross

Micross is the leading one-source, one-solution provider of Bare Die & Wafers, Advanced Interconnect Technology, Custom Packaging & Assembly, Component Modification Services, Electrical & Environmental Testing and Hi-Rel Products to manufacturers and users of semiconductor devices. In business for more than 35 years, our comprehensive array of high-reliability capabilities serve the global Defense, Space, Medical, Industrial and Fabless Semiconductor markets. Micross possesses the sourcing, packaging, assembly, test and logistics expertise needed to support an application throughout its entire program cycle.

 

About Micross Advanced Interconnect Technology

Micross Advanced Interconnect Technology offers advanced packaging and 3D integration solutions that enable higher-performance systems with decreased size, weight, and power (SWaP). We provide a wide variety of advanced interconnect technologies for realizing your next-generation electronic systems inclusive of flip-chip and wafer-level packaging, through-silicon vias (TSV), through-glass vias (TGV), high-density (fine-pitch) interconnects and fabrication of Si or glass interposers. Micross AIT houses an ITAR-registered, state-of-the-art microfabrication facility that allows us to provide development, custom (flexible) prototyping and production services for our customers.

 

Micross Contact Information:

Valerie Thomas, Marketing Manager

Valerie.thomas@micross.com

 

 

 

Nov 30 AIT 3D ASIP PR