Mixed Signal Test Partnership
Our mixed signal test development, test translation and test verification expertise provides VLSI IC designers with a partnered approach for productivity improvement.
- Shorter development cycle
- Improved supply chain efficiency
- Reduced overall development costs
- Maximized reliability & test coverage
How do we do this?
- Use of industry standard STIL format with project specific support documentation for IC designers
- Partnership at early development cycle to establish appropriate test coverage for given timescale & budget
- Pre-planning of test protocol to ensure forward compatibility with supply chain ATE
- Translation of simulation data into realisable & practical test software
- Verification testing of initial chip spins and collaborative feedback for next generation
- Maximization and finalization of test solution based on a given system and future plan
IC Design Support → Project Planning → Test Development → Test Verification + Modification → Finalized Test Solution + Platform
Typical VLSI Technical Capability
For all VLSI testing (high pin-count digital, mixed-signal and analog devices), Micross currently uses LTX-Credence platfoms.
The following provides a typical example of our capability, whereas detailed technical system/setups can also be specified for your specific application.
- 288 digital IO channels, each with its own parametric subsystem
- Functional testing digital devices and also allows for scan testing if required
- Independent parametric measurement unit (PMU) per pin
- Independent level/timing/format generator per pin
- Test vector depth is configured to 16Mb per pin, having an instruction rate of 100MHz and the vector memory has full scan-vector capability, all of which ensures that the D10 can cope with the most complex of digital parts
- Digital vector of speeds up to 200M bits/sec are possible using clock doubling
- Multiple scan paths can be used to a maximum pattern depth of 1152M
- The STIL format for test vectors (patterns) and timing is supported by most ASIC design suites so integration into our test environment is a one-step process
- 16 independent voltage/current source units for device power or analog input/output
- Can source/measure ±20V @ 300mA or ±60V @ 100mA
- 8,000 samples of waveform generation per channel
- 1,000 samples of waveform capture memory per channel
- 16-bits accuracy @ 100k samples per second (kS/s)
- 6 timers per channel with 100nS resolution
- Four arbitrary waveform generator and data capture units for high frequency analog signals
- High precision (audio) 24-bit ADC/DAC to a maximum of 768 kS/s
- High frequency (video) 16-bit ADC/DAC to a maximum of 250 MS/s
- Independent PMU per channel
- Synchronization between digital and analog subsections is controlled from the digital test pattern so that analog events can be timed to trigger under full synchronous control from the test program to enable testing of embedded ADCs and DACs within the ASIC.
- DSP of captured waveforms is performed in C++ so analysis algorithms can be implemented as required (DFT/FFT, PDF histograms, filtering, etc.)
- Comprehensive test software suite based upon industry standard STIL (IEEE 1450) and C++, operating on a Linux-based PC platform
Since only a sub-set of the STIL format is required to enable a test program to be produced, details of our tester-specific requirements are available on request.