Wafer Level Programming
Wafer Level Programming of Semiconductor Die
A large majority of bare die are designed with a predetermined, repeatable and fixed function. However there are specialised families of die which are designed to be customisable and programmable. Programming of these components tends in the most part to be done at the fully assembled package level. However in the case of bare die there is need for specialist expertise to program both in terms of interfacing wafer probe / test / programming equipment together and also with the delicacy and need for highest accuracy handling unencapsulated bare die material.
Analog
In the Analog world the majority of programming is usually where ICs receive a "trim" of certain parameters to give a higher degree of accuracy or performance than can be achieved by the initial wafer construction process. There are 2 main approaches to calibrating an analog bare die:
- Laser Trim - Which is intended to adjust the physical features on the chip within a much smaller tolerance than is available at wafer fab and design. The Laser trim process often is included as part of the wafer flow and requires specialist equipment that is both costly and requires expertise. This is not something we perform in-house
- Zener-Zap - This is a common approach and is where we can assist to program your analog bare die. Zener-Zap construction uses an array of zener diodes is directly connected by design to a given output parameter. The connected diodes are then "Zapped" using set programming protocols to physically blow a certain number of diodes. As selected diodes are physically destroyed then the mean blocking potential on the flow of electricity is changed which allows the user to calibrate the output parameter within a tighter tolerance window than was capable within the original design rules of the fab process itself. In short controlling the number of active/inactive zener diodes allows a one-time calibration so all zener zap ICs begin which a full complete array of zeners ready for calibration. The process of Zener Zap is also popular for packaged components as can be done using lower cost equipment as opposed to Laser Trimming and also can be done in fully encapsulated package form which takes away some of the handling sensitivity. At die level Zener-Zap is still a challenge but we have the necessary experience and understanding to make it viable and productionable for bare die customers
Digital
Non-Volatile Memory is the most common product to be programmed, this can be achieved by a straight forward load of information or similar to the Zener-Zap technique can mean taking a volatile memory and blowing certain gates or connections to make it's programming non-volatile, known as "Anti-Fuse". Again the majority is programmed in package form but there are specialist applications that require die level. At die level the objective is to interface the wafer prober with the programmer to successfully make connection with each die, program it and then also test it. Here at Micross we carry programmers capable of handling most digital components. Where security, specialist algorithms or encryption are required we are willing to work with both the original manufacturer of the die and also the end customer to ensure that all requirements are met. Often customers may wish to use die programming to make variants of the same device on one wafer, this gives them scope to offer customisable solutions / products depending on the end customer specification. We retain traceability to single die to make this possible.
In summary we offer a flexible engineering capability for both R&D and production quantities which is customisable to your requirements.
Wafer Level Programming - Capabilities
- Antifuse, Low Voltage, PROM, EPROM, EEPROM, FLASH, MCU, GAL, PAL, PIC, FPGA, Zener Zap Trimming
- Majority of programming formats supported
- Custom setups developed
- Traceability to wafer & single die where required
- Multiple programs per wafer
Customisable output data and logging