Chip Scale Package (CSP)

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Save valuable PCB real estate with
Chip Scale Packaging from Micross.

Chip scale technologies have common attributes of minimal size, no more than 1.2X the area of the original die size, and are direct surface mountable.
Source: IPC/JEDEC J-STD-012 (PDF)

Chip Scale Package (CSP)We're here to meet your application's demand for a smaller, more reliable packaged component with our chip scale packaging solutions. Chip scale packages offer near-die size footprints and reductions to package thickness and weight.

The best of both worlds. A chip scale package combines the performance and size advantages of flip chip bare die and the reliability of an encapsulated device in one tiny package. Chip scale packaging is the ideal solution for battery powered small form factor devices such as wearable/hand-held electronics, implantable/non-implantable medical devices, industrial sensors and a variety of military applications.

CSP Space Savings DiagramKey Features

  • Flexible tooling for custom packages
  • Single die design typically 20% larger than die size
  • 0.5mm pitch up to 1.27mm pitch
  • Capable of package heights <1mm
  • MSL level 3 capable


  • Die attach - 100μm min die thickness, 10μm min placement accuracy
    • Epoxy - conductive, nonconductive, cyanate ester (die size: 250μm min / 20mm max)
    • Solder - die size: 250μm min / 20mm max
  • Flip chip - eutectic, lead-free, high lead; 75μm min bump height, 150μm min bump pitch
  • Die stacking - up to four die high
    • Pyramid, cantilever and equal size die
  • Wire Bond
    • Ball/wedge bonding (0.7 – 2.0 mil Al or Au wire; 45μm min pitch)
    • Wedge/wedge (0.7 – 2.0 mil Au wire; 45μm min pitch)
    • Heavy gauge wedge/wedge (5.0 – 20 mil Al wire)
  • Lid seal - ceramic, metal, plastic
  • Encapsulation - transfer mold, potting, dam & fill
  • Marking - ink pad transfer or laser marking
  • Lead finishing - Au, eutectic, or lead-free solder

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